In multiple-clock domain communication systems that transmit data between multiple agents, each agent may receive data from other agents operating at frequencies and phases different from its own. FIG. 1 illustrates a conventional multiple-clock domain communication system 100, which includes transmitting agents 101, 102 and 10N, each of which operates based on clock signals CLK_1, CLK_2 and CLK_N, respectively, which may have different frequencies and/or phases (i.e., are asynchronous).
Transmitting agents 101, 102 and 10N provide J-bit write data values WD_1, WD_2 and WD_N, respectively, write enable control signals WC_1, WC_2 and WC_N, respectively, and clock signals CLK_1, CLK_2 and CLK_N, respectively, to FIFOs 301, 302 and 30N, respectively, within receiving agent 20. FIFOs 301, 302 and 30N are controlled to buffer and resynchronize the received data WD_1, WD_2 and WD_N within receiving agent 20. More specifically, downstream processing unit 40 monitors the contents of FIFOs 301, 302 and 30N. In response, downstream processing unit 40 provides read enable control signals RC_1, RC_2 and RC_N (along with local clock signal CLK_P) to FIFOs 301, 302 and 30N, respectively, thereby initiating read accesses to FIFOs 301, 302 and 30N, wherein previously stored data values WD_1, WD_2 and WD_N are provided to downstream processing unit 40 in synchronism with the local clock signal CLK_P (which may have a different frequency/phase than clock signals CLK_1, CLK_2 and CLK_N). In response, downstream processing unit 40 provides an output data stream DOUT.
Throughput (TP) is defined as the amount of data transferred through or processed by an agent over a given time. The receiving agent 20 has a maximum throughput of T. The peak throughput of each incoming data stream (WD_1, WD_2 and WD_N) can typically be as high as that of the output data stream DOUT (i.e., T), for predetermined limited time periods. Flow control circuitry 21 in the receiving agent 20 controls flow control circuitry 111, 112 and 11N in transmitting agents 101, 102 and 10N, respectively, such that the average throughput of the transmitting agents 101, 102 and 10N (i.e., the average throughput of the input data buses to FIFOs 301, 302 and 30N) is less than or equal to the maximum throughput T of receiving agent 20. For example, the flow control circuitry 21 may cause each of the flow control circuits 111, 112 and 11N to limit the throughput of its corresponding data stream to an average throughput equal to the maximum throughput T of the receiving agent 20 divided by the number of incoming data streams, N. Although the average throughput of each of the incoming data streams is limited, it is possible that one or more of the incoming data streams may be providing write data at the maximum throughput T at the same time. At this time, one of the incoming data streams WD_1, WD_2 and WD_N may be temporarily allocated all of the transfer resources within the downstream processing unit 40, while the other incoming data stream(s) are buffered in their corresponding FIFOs.
The required number of entries (K1, K2 and KN) in each of the FIFOs 301, 302 and 30N is determined by several factors, including: the number of entries (A) required to resynchronize the (asynchronous) incoming data values with the local clock signal CLK_P; the number of entries (B) required to buffer incoming data values during the transient periods when the sum of the throughputs of the incoming data streams exceeds the maximum throughput (T) of the downstream processing unit 40; the number of entries (C) required to buffer the incoming data values for the duration of a worst case wait time (TWAIT) associated with the downstream processing unit 40 (i.e., the maximum time allowed between the time data is written to a FIFO and the time downstream processing unit 40 must begin reading data from the FIFO); and the number of entries (D) required to buffer the incoming data values from the time the flow control circuitry 21 sends a flow control message, and the time the flow control circuitry 111, 112 and 11N responds to the flow control message (e.g., by temporarily curtailing the transmission of data values).
The number of entries (A) is relatively small, and depends on the frequencies of the various clock signals CLK_1, CLK_2, CLK_N and CLK_P, as well as clock jitter and the set up and hold times of the memory used to implement the FIFOs 301, 302 and 30N.
The number of entries (B) depends on the frequencies of the various clock signals CLK_1, CLK_2, CLK_N and CLK_P, as well as the flow control methods implemented by flow control circuitry 21, and in particular, on the allowed durations of the temporary periods during which the sum of the throughputs of the incoming data streams may temporarily exceed the maximum throughput of the downstream processing unit 40.
The number of entries (C) is typically relatively large, and depends on the worst case wait time (TWAIT) allowable before the downstream processing unit 40 must start reading data previously stored in the FIFOs 301, 302 and 30N. Note that if the worst case wait time (TWAIT) of one of the FIFOs 301, 302 and 30N elapses without previously stored data being transmitted from this FIFO, flow control circuitry 21 will transmit a back-off message to the flow control circuitry of the associated transmitting agent, instructing this transmitting agent to temporarily stop transmitting data to receiving agent 20. The worst case wait time TWAIT requires an additional C=TWAIT*T entries in each of the FIFOs 301, 302 and 30N. The worst case wait time TWAIT is defined by the required operations of the downstream processing unit 40, and typically requires hundreds or thousands of entries within each of the FIFOs 301-30N.
The number of entries (D) is typically smaller than the number of entries (C), and depends on the time that elapses between the time the flow control circuitry 21 transmits a back-off message to a transmitting agent, and the time that the transmitting agent responds to the back-off message by stopping data transmission. This time period is referred to as the flow control response time (TF), which requires an additional D=TF*T entries in each of the FIFOs 301, 302 and 30N.
Depending on system requirements and agent design limitations, the FIFO depth requirements of FIFOs 301, 302 and 30N (i.e., the required number of entries, K1, K2 and KN for FIFOs 301, 302 and 30N, respectively) may be very large (e.g., hundreds or thousands of entries for each FIFO). This is an inefficient use of FIFO resources, just to cover a worst case possibility. It would therefore be desirable to reduce the required depths of FIFOs 301, 302 and 30N.
Depending on system requirements and agent design limitations, the distances between transmitting agents 101, 102 and 10N and receiving agent 20 may be relatively long. Similarly, long routes may exist between FIFOs 301, 302 and 30N and downstream processing unit 40. The long routes described above require that the associated buses (e.g., the buses between transmitting agents 101, 102 and 10N and FIFOs 301, 302 and 30N, and the buses between FIFOs 301, 302 and 30N and downstream processing unit 40) are implemented in the multi-layer metal interconnect structure of the associated integrated circuit chip. Note that each of the buses between FIFOs 301, 302 and 30N and downstream processing unit 40 must be designed to meet the maximum throughput T of downstream processing unit 40. This is an inefficient use of the available interconnect resources, and can result in the design of communication system 100 becoming impractical due to performance, routing and die size constraints. It would therefore be desirable to reduce the number/length of buses of communication system 100 that must be implemented using the multi-layer metal interconnect resources of an integrated circuit chip.